VIPEER

Boosting SVM Based Traffic Classification:
New Architectural Design Directions, Massive Parallelization on GPU and Hardware Acceleration on FPGA

Abstract

Understanding the composition of the Internet traffic has many applications nowadays mainly tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Although many classification methods such as the Support Vector Machine (SVM) algorithm have proven their accuracy, no enough attention has been given to the practical implementation of a classification architecture and to the investigation of the stability of the approaches to different networks. In this paper, we consider the real implementation of the SVM method by considering three main challenges: (i) adapting the training datasets to the composition of the traffic in the real network. The collaboration of a small set of end-users allows to construct stable traffic models. (ii) dealing with high rate traffic to do online detection of category of applications. Our solution is based on a hardware acceleration of the SVM classification on a NetFPGA board. (iii) As training models must be adapted regularly, the training phase of the SVM method must be optimized. Therefore, we design and implement a software version that is massively parallelized on a Graphical Processing Unit (GPU).

Code and documentation

Community-based distributed classification architecture

Detection plane:

Detection Client : code and documentation (on demand).
Detection Collector: code and documentation (on demand)
Detection Process: code and documentation (on demand)
Detection web interface : code and documentation (coming soon)

Learning plane:

System calls Analysis module: code and documentation (coming soon)
Learning capture client: code and documentation (coming soon)
Trace constructor: code and documentation (coming soon)
Learning Process: code and documentation (coming soon)
Learning web interface: code and documentation (coming soon)

NetFPGA hardware acceleration of SVM based classifier

Verilog code of the NetFPGA implementation (on demand)
Documentation (coming soon)

Parallelization of the SVM training algorithm

OpenMP implementation of the SVM classification library: documentation and code (on demand)
GPU accelerated SVM training: code and implementation (on demand)

Contributors

Tristan Groléat, TELECOM Bretagne, France (tristan.groleat@telecom-bretagne.eu)

Sébastien Martinez, TELECOM Bretagne, France (sebastien.martinez@telecom-bretagne.eu)

Mohamed Karim Sbai, TELECOM Bretagne, France (mohamed.sbai@telecom-bretagne.eu)

Sandrine Vaton, TELECOM Bretagne, France (sandrine.vaton@telecom-bretagne.eu)

Serge Guelton, TELECOM Bretagne, France (serge.guelton@telecom-bretagne.eu)

Matthieu Arzel, TELECOM Bretagne, France (matthieu.arzel@telecom-bretagne.eu)

Contact person