Error-correction codes are used in the vast majority of communication systems because they allow a significant reduction of the transmitter power. Although many different coding schemes that can approach the Shannon limit on transmit power are known, the capability of practical systems is often limited by the energy consumption of the decoder. This constraint is being mentioned as a key performance metric in the ongoing 5G standardization process in order to deal with the great increase in the number of users and in the throughput while keeping a constant energy budget. In addition to the practical need for low-energy receivers, recent theoretical results have shown that in order to get arbitrarily close to the Shannon limit, the decoding circuit must consume an arbitrarily large amount of energy. This shows that optimizing the trade-off of coding gain versus decoding energy is fundamental in the channel coding problem.

EF-FECtive aims to develop low-density parity-check (LDPC) codes and decoder circuits that together provide a 10x reduction in the energy consumption of decoders, while preserving equivalent communication performance. This will be achieved through contributions to both communication theory and VLSI system design, with the ultimate objective of demonstrating a decoder ASIC that can tolerate circuit faults while operating in the energy-efficient near-threshold regime.

First, an approach to model the energy consumption of LDPC decoders combining an analysis of the decoding algorithm with simulations of circuit models will be developed. Based on these energy models, theoretical tools will be created to design LDPC codes and decoder circuits that minimize the decoding energy. Then, decoder implementations operated in the near-threshold regime will be studied. In this regime, extremely energy-efficient operation can be achieved, but maintaining fast processing performance requires the system to tolerate faulty computations. By developing accurate models of the effect of faults on the decoder and of its energy consumption, methods will be proposed to jointly optimize the LDPC code construction, the implementation parameters, and the amount of circuit faults allowed to drastically reduce the decoding energy. Finally, an ASIC prototype of the decoder will be designed, fabricated and tested to demonstrate the energy gains in practice.

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